The present invention relates to a layout technique of semiconductor integrated circuits, and particularly to a technique which is effective when applied to the circuit design of portable devices such as a cellular phone and a Personal Digital Assistant (PDA).
In the circuit design of portable devices such as a cellular phone and a PDA for which demand is increasing recently, reduction of power consumption has become essential. The technique of dividing a logical block on a chip into several groups and performing ON/OFF control of power source for each group is effective in reducing power consumption. A group of logical blocks operating at a single power source voltage level is referred to as the “power domain”, and a physical placement area of the logical block operating at the single power source voltage level is referred to as the “voltage island”.
Japanese Patent Laid-Open No. 2008-176486 (Patent document 1) describes a method of generating a voltage island at an operation synthesis level or a function design level such as Register Transfer Level (RTL). According to Patent document 1, area, timing and power consumption are estimated at the function design level and the voltage island is generated based on the estimated value. In improving timing violation or reducing area at the function design level, improvement is attempted by assigning a higher value to the power source voltage value. In addition, in reducing power consumption, improvement is attempted by assigning a smaller value to the power source voltage. A voltage island is generated, and the influence by the provision of the voltage island is fed back to the operation synthesis process. Accordingly, a circuit which has been optimized in terms of timing, area, and power consumption can be obtained in a short period.